AMD CCD Architecture

AMD CCD Architecture

The Core Complex Die, or CCD, is the fundamental building block of AMD's modern CPUs. Each CCD is a small chip that contains up to 8 CPU cores, their associated cache, and the infrastructure needed to communicate with other chiplets. By combining multiple CCDs with an I/O die, AMD can create CPUs with different core counts from the same basic building blocks.

Inside a CCD, the cores are organized into Core Complexes, or CCXs. In Zen 2 and Zen 3, each CCX had 4 cores sharing 16 MB of L3 cache. Starting with Zen 4, AMD moved to a single CCX per CCD with 8 cores sharing 32 MB of L3 cache. This simplified the architecture and reduced latency because all cores in a CCD could access the same L3 cache without crossing chiplet boundaries.

Communication between CCDs happens through the Infinity Fabric, which runs through the I/O die. When a core in CCD 0 needs data that is cached in CCD 1, the request has to travel from CCD 0 to the I/O die, then to CCD 1, and the data has to travel back the same way. This adds latency compared to accessing data within the same CCD. This is why some workloads scale better with more cores than others.

AMD uses a technique called core parking to manage this. The operating system's scheduler tries to keep related threads on the same CCD to minimize cross-chiplet communication. Windows and Linux both have optimizations for AMD's chiplet architecture. In gaming, this means the game and its critical threads are kept on one CCD, while background tasks run on the other.

The number of CCDs determines the maximum core count. A Ryzen 5 has one CCD with 6 cores enabled. A Ryzen 7 has one CCD with 8 cores. A Ryzen 9 has two CCDs for 12 or 16 cores. A Threadripper can have up to 8 CCDs for 96 cores. The chiplet design makes this scaling possible without designing a completely new chip for each product. It is the same reason AMD can offer so many different CPU models from the same basic design.